Advances in semiconductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and/or complete systems on individual integrated circuits. Additionally, as the density of integrated circuits has grown, the power requirements for computing systems (from embedded systems to servers) have also escalated. Furthermore, software inefficiencies, and its requirements of hardware, have also caused an increase in computing device energy consumption. In fact, some studies indicate that computing devices consume a sizeable percentage of the entire electricity supply for a country, such as the United States of America. As a result, there is a vital need for energy efficiency and conservation associated with integrated circuits. These needs will increase as servers, desktop computers, notebooks, ultrabooks, tablets, mobile phones, processors, embedded systems, etc. become even more prevalent (from inclusion in the typical computer, automobiles, and televisions to biotechnology).
In conventional power management techniques, the power consumption of a multi-core processor can be reduced by monitoring the processor activity of each central processor unit (CPU) core and to power down a CPU core when that particular CPU core is idle. In a multi-core processor architecture, the last level cache (LLC) is shared by all CPU cores. As each CPU core can be independently powered down into a low power state, parts of the LLC can also be powered down to shrink the LLC size to further reduce power consumption. This is because with less CPU cores that are active, less LLC is expected to be needed. Hence, in these power management techniques, the LLC is resized based on the processor activity of the CPU cores in the processor. While this approach reduces the power consumption when one or more CPU cores are idle in a low power state, this approach only shrinks the LLC when the processor is in a low activity state (e.g., when one or more CPU core is idle), and does not provide any power savings when all CPU cores in the processor are active.